This web page examines trap generating instructions in assembly language. Specific examples of instructions from various processors are used to illustrate the general nature of assembly language.
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Trap generating instructions generate an exception that transfer control from software (usually application programs) to the operating system.
Operating system traps provide a mechanism to change to higher privilege levels (if they exist on the processor) and usually include a mechanism for identifying what kind of trap has occurred. This allows application programs to make requests of the operating system and may provide a hardware mechanism for switching from a user mode to a superviser, kernel, or other higher privilege level for the operating system response to the request.
A breakpoint instruction is used with external debugging hardware. The breakpoint instruction replaces an ordinary instruction (or the first part of an instruction) and relies on external debugging hardware to supply the missing instruction (or part of an instruction).
Various check instructions will test for conditions, trapping if the test fails. One common example is a check against bounds or limits.
Most processors have one or more illegal instructions. These are usually instructions that haven’t been implemented yet or instructions that have been dropped from a processor line. Many processors generate a trap or exception upon encountering an illegal instruction. Some processors will execute illegal instructions, which can lead to undocumented operations. Undocumented operations tend to change from one batch of processors to another and are highly unreliable. Some processors reserve an opcode that is guaranteed to always be illegal and always generate a trap or exception.
TRAP Trap; Motorola 680x0, Motorola 68300; generates a trap exception with a trap vector (32 plus an immediate value in the range of 0 to 15); does not modify flags
TRAPcc Trap on Condition; Motorola 680x0, Motorola 68300; if the tested condition is ture, generates a trap exception with vector 7, with optional word (16-bits) or longword (32-bits) immediate operand being available for the software trap handler: TRAPCC, TRAPCS, TRAPEQ, TRAPF, TRAPGE, TRAPGT, TRAPHI, TRAPLE, TRAPLS, TRAPLT, TRAPMI, TRAPNE, TRAPPL, TRAPT, TRAPVC, TRAPVS
Axxx A-line Trap; Motorola 680x0, Motorola 68300; generates an a-line trap with the 12 bit value in the byte and a half of the instruction word used as a vector into a trap table; reserved for use by computer hardware manufacturers to provide software routines or implement supporting hardware features (used in the Macintosh to provide operating system calls); does not modify flags
BKPT Breakpoint; Motorola 680x0, Motorola 68300; asserts a breakpoint acknowledge bus cycle with an immediate breakpoint vector (0 to 7) on address lines A2-A4 (not to be confused with address registers), if external hardware terminates the cycle, the data (one instruction word) on the bus is inserted into the instruction pipe, otherwise generates an illegal instruction exception; does not modify flags
CHK Check Register Against Bounds; Motorola 680x0, Motorola 68300; compares a word (16-bits) or longword (32-bits) value in a data register to a lower bound of zero and a two’s complement upper bound specified in a data register or memory, a value of less than zero or greater than the upper bound results in a CHK instruction exception, vector number 6; sets or clears flags
CHK2 Check Register Against Two Bounds; Motorola 680x0, Motorola 68300; compares a byte (8-bits), word (16-bits), or longword (32-bits) value in a data or address register to a bounds pair specified in memory, a value of less than the lower bound or greater than the upper bound results in a CHK instruction exception, vector number 6; sets or clears flags
BOUND Check Array Index Against Bounds; Intel 80x86; compares the contents of register (16 or 32 bits) to a bounds pair (lower bound followed by upper bound) in memory (source register contains address in memory of the first of two consecutive bounds), if the check fails, then an Interrupt 5 occurs; does not modify flags
ILLEGAL Take Illegal Instruction Trap; Motorola 680x0, Motorola 68300; generates an illegal instruction exception, vector 4; does not modify flags
TRAPV Trap; Motorola 680x0, Motorola 68300; if the overflow condition is set, generates a TRAPV exception, vector 7; does not modify flags
INT Interrupt; Intel 80x86; pushes flags register and return address on stack and then generates a software call to the interrupt handler designated by the immediate operand (0 to 255) as in index into the Interrupt Descriptor Table (IDT), in Protected Mode the IDT is an array of eight-byte descriptors, in Real Address Mode the IDT is an array of doubleword (32 bit) pointers, the first 32 entries are reserved to Intel (matching hardware interrupts and exceptions), the base address of the IDT is the contents of the IDTR
INTO Interrupt if Overflow; Intel 80x86; if the Overflow flag is set, pushes flags register and return address on stack and then generates a software call to the fourth (4) interrupt handler in the Interrupt Descriptor Table (IDT), in Protected Mode the IDT is an array of eight-byte descriptors, in Real Address Mode the IDT is an array of doubleword (32 bit) pointers, the first 32 entries are reserved to Intel (matching hardware interrupts and exceptions), the base address of the IDT is the contents of the IDTR
IRET Return From Interrupt; Intel 80x86; transfers the value at the top of the system stack into the flags register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer, and changes program flow to the return address; optional immediate operand added to the new top-of-stack pointer, effectively removing any arguments that the calling program pushed on the stack before the execution of the corresponding CALL instruction; possible change to lesser privilege
RTE Return from Exception; Motorola 680x0, Motorola 68300; transfers the value at the top of the system stack into the status register, increments the system stack pointer, fetches the return address from the top of the system stack, increments the system stack pointer by a displacement value designated by format mode (effectively deallocating temporary storage space from the stack, the amount of space varying by type of exception that occurred), and changes program flow to the return address; privileged instruction (supervisor state)
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