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# Assembly Language

## summary

This web page examines integer arithmetic instructions in assembly language. Specific examples of instructions from various processors are used to illustrate the general nature of assembly language.

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### integer arithmetic

For most processors, integer arithmetic is faster than floating point arithmetic. This can be reversed in special cases such digital signal processors.

The basic four integer arithmetic operations are addition, subtraction, multiplication, and division. Arithmetic operations can be signed or unsigned (unsigned is useful for effective address computations). Some older processors don’t include hardware multiplication and division. Some processors don’t include actual multiplication or division hardware, instead looking up the answer in a massive table of results embedded in the processor.

A specialized, but common, form of addition is an increment instruction, which adds one to the contents of a register or memory location. For address computations, “increment” may mean the addition of a constant other than one. Some processors have “short” or “quick” addition instructions that extend increment to include a small range of positive values.

A specialized, but common, form of subtraction is an decrement instruction, which subtracts one from the contents of a register or memory location. For address computations, “decrement” may mean the subtraction of a constant other than one. Some processors have “short” or “quick” subtraction instructions that extend decrement to include a small range of values.

Compare instructions are used to examine one or more integers non-destructively. These are usually implemented by performing a subtraction in some shadow register or accumulator and then setting flags accordingly. Compare instructions can compare two integers, or can compare a single integer to zero. Triadic compare instructions compare a test value to an upper and lower limit, which can be useful for bounds and range checking.

Some processors have specific hardware support for large multi-byte integer arithmetic. Even if there is no specific support, generally carry and borrow flags can be used to implement software multi-byte arithmetic routines.

Some processors have other special integer arithmetic operations. A clear instruction sets a register or memory location to zero. Some processors have special instructions for setting a register to a special value (such as pi) with additional guard bits also being set appropriately. A sign extend operation takes a small value and sign extends it to a larger storage format (such as byte to word). An arithmetic complement gives the arithmetic complement of a number (one’s complement). An arithmetic negate gives the arithmetic inverse of a number (subtract from zero; two’s complement).

• ADD Add Integers; Intel 80x86; integer add of the contents of a register or memory (8, 16, or 32 bits) to a memory location or a register; sets or clear flags
• ADD Add; Motorola 680x0, Motorola 68300; signed add of the contents of a data register (8, 16, or 32 bits) to a memory location or adds the contents of a memory location (8, 16, or 32 bits) to a data register; sets or clear flags
• ADD Add Wide; ARM (Thumb 2); Integer add of right rotated immediate constant and Register n with result stored in register d
• ADD Add; MIX; add word or partial word field contents of memory to A-register (accumulator), overflow toggle set if result is too large for A-register
• AR Add Register; IBM 360/370; RR format; signed add of the contents of a general purpose register (32 bits) to a general purpose register (32 bits); register to register only; sets or clears flags
• A Add; IBM 360/370; RX format; signed add of the contents of a memory location (32 bits) to a general purpose register (32 bits); main memory to register only; sets or clears flags
• AH Add Half-word; IBM 360/370; RX format; signed add of the contents of a memory location (16 bits) to a general purpose register (low order 16 bits); main memory to register only; sets or clears flags
• ADDA Add Address; Motorola 680x0, Motorola 68300; unsigned add of the contents of a memory location or register (16 or 32 bits) to an address register; does not modify flags
• ADDI Add Immediate; Motorola 680x0, Motorola 68300; signed add of immediate data (8, 16, or 32 bits) to a register or memory location; sets or clears flags
• ADDQ Add Quick; Motorola 680x0, Motorola 68300; signed add of an immediate value of 1 to 8 inclusive to a register or memory lcoation; sets or clears flags for data registers and memory locations, does not modify flags for an address register
• INC Increment; DEC VAX; increments the integer contents of a general purpose register or contents of memory (INCB byte, INCW word, INCL longword); equivalent to ADDx2 #1, sum, but shorter and executes faster; clears or sets flags
• INC Increment by 1; Intel 80x86; increments the contents of a register or memory (8, 16, or 32 bits); sets or clear flags (does not modify carry flag)
• ADWC Add With Carry; DEC VAX; integer addition (32 bit) in general purpose registers or memory, first operand added to second operand and the C (carry) flag with result replacing second operand; used for multiprecision arithmetic; clears or sets flags
• ADC Add Integers with Carry; Intel 80x86; integer add of the contents of a register or memory (8, 16, or 32 bits) and the carry flag to a memory location or a register, used to implement multi-precision integer arithmetic; sets or clear flags
• ADC Add with Carry; ARM; Integer add of operand2 and Register n and Carry with result stored in register d; conditionally executed; optionally updates flags
• ADDX Add Extended; Motorola 680x0, Motorola 68300; (signed add of a data register [8, 16, or 32 bits] and the extend bit to a data register) or (signed add of the contents of memory location [8, 16, or 32 bits] and the extend bit to the contents of another memory location while predecrementing both the source and destination address pointer registers), used to implement multi-precision integer arithmetic; sets or clears flags
• ADAWI Add Aligned Word Interlocked; DEC VAX; adds (16 bit integer) a source operand from a register or memory to a memory location that is word aligned while interlocking the memory location so that no other processor or device can read or write to the interlocked memory location, used to maintain operating system resource usage counts; and sets or clears flags
• SUB Subtract; DEC VAX; signed subtraction of scalar quantities (8, 16, or 32 bit integer) in general purpose registers or memory, available in two operand (first operand subtracted from second operand with result replacing second operand) and three operand (first operand subtracted from second operand with result placed in third operand) (SUBB2 subtract byte 2 operand, SUBB3 subtract byte 3 operand, SUBW2 subtract word 2 operand, SUBW3 subtract word 3 operand, SUBL2 subtract long 2 operand, SUBL3 subtract long 3 operand); clears or sets flags
• SUB Subtract Integers; Intel 80x86; integer subtraction of the contents of a register or memory (8, 16, or 32 bits) from a memory location or a register; sets or clear flags
• SUB Subtract; Motorola 680x0, Motorola 68300; signed subtract of the contents of a data register (8, 16, or 32 bits) from a memory location or subtracts the contents of a memory location (8, 16, or 32 bits) from a data register; sets or clear flags
• SUB Subtract; MIX; subtract word or partial word field contents of memory from A-register (accumulator), overflow toggle possibly set
• SR Subtract Register; IBM 360/370; RR format; signed subtract of the contents of a general purpose register (32 bits) from a general purpose register (32 bits); register to register only; sets or clears flags
• S Subtract; IBM 360/370; RX format; signed subtract of the contents of a memory location (32 bits) from a general purpose register (32 bits); main memory to register only; sets or clears flags
• SH Subtract Half-word; IBM 360/370; RX format; signed subtract of the contents of a memory location (16 bits) from a general purpose register (low order 16 bits); main memory to register only; sets or clears flags
• SUBA Subtract Address; Motorola 680x0, Motorola 68300; unsigned subtract of the contents of a memory location or register (16 or 32 bits) from an address register; does not modify flags
• SUBI Subtract Immediate; Motorola 680x0, Motorola 68300; signed subtract of immediate data (8, 16, or 32 bits) from a register or memory location; sets or clears flags
• SUBQ Subtract Quick; Motorola 680x0, Motorola 68300; signed subtract of an immediate value of 1 to 8 inclusive from a register or memory lcoation; sets or clears flags for data registers and memory locations, does not modify flags for an address register
• DEC Decrement; DEC VAX; decrements the integer contents of a general purpose register or contents of memory (DECB byte, DECW word, DECL longword); equivalent to SUBx2 #1, sum, but shorter and executes faster; clears or sets flags
• DEC Decrement by 1; Intel 80x86; decrements the contents of a register or memory (8, 16, or 32 bits); sets or clear flags (does not modify carry flag)
• SBWC Subtract With Carry; DEC VAX; integer subtraction (32 bit) in general purpose registers or memory, first operand and the C (carry) flag subtracted from second operand with result replacing second operand; used for extended precision subtraction; clears or sets flags
• SBB Subtract Integers with Borrow; Intel 80x86; integer subtraction of the contents of a register or memory (8, 16, or 32 bits) and carry flag from a memory location or a register; sets or clear flags
• SUBX Subtract Extended; Motorola 680x0, Motorola 68300; (signed subtract of a data register [8, 16, or 32 bits] and the extend bit from a data register) or (signed subtract of the contents of memory location [8, 16, or 32 bits] and the extend bit from the contents of another memory location while predecrementing both the source and destination address pointer registers), used to implement multi-precision integer arithmetic; sets or clears flags
• MUL Multiply; DEC VAX; signed multiplication of scalar quantities (8, 16, or 32 bit integer) in general purpose registers or memory, available in two operand (first operand multiplied by second operand with result replacing second operand) and three operand (first operand multiplied by second operand with result placed in third operand) (MULB2 multiply byte 2 operand, MULB3 multiply byte 3 operand, MULW2 multiply word 2 operand, MULW3 multiply word 3 operand, MULL2 multiply long 2 operand, MULL3 multiply long 3 operand); clears or sets flags
• MULS.W Signed Multiply; Motorola 680x0, Motorola 68300; signed multiplication of a word (16 bits) from memory or a register by a word (16 bits) in a data register with a longword (32 bit) result stored in the entire data register; sets or clears flags
• MULS.L Signed Multiply; Motorola 680x0, Motorola 68300; signed multiplication of a longword (32 bits) from memory or a register by a longword (32 bits) in a data register with a longword (32 bit) result stored in the data register (high order 32 bits of product are discarded); sets or clears flags
• MULS.L <ea>,Dh:Dl Signed Multiply; Motorola 680x0, Motorola 68300; signed multiplication of a longword (32 bits) from a data register by a longword (32 bits) in a data register with a quadword (64 bit) result stored in the data registers (high order 32 bits of product in first register, low order 32 bits of product in second data register); sets or clears flags
• MULU.W Unsigned Multiply; Motorola 680x0, Motorola 68300; unsigned multiplication of a word (16 bits) from memory or a register by a word (16 bits) in a data register with a longword (32 bit) result stored in the entire data register; sets or clears flags
• MULU.L Unsigned Multiply; Motorola 680x0, Motorola 68300; unsigned multiplication of a longword (32 bits) from memory or a register by a longword (32 bits) in a data register with a longword (32 bit) result stored in the data register (high order 32 bits of product are discarded); sets or clears flags
• MULU.L <ea>,Dh:Dl Unsigned Multiply; Motorola 680x0, Motorola 68300; unsigned multiplication of a longword (32 bits) from a data register by a longword (32 bits) in a data register with a quadword (64 bit) result stored in the data registers (high order 32 bits of product in first register, low order 32 bits of product in second data register); sets or clears flags
• MUL Unsigned Multiplication of AL or AX; Intel 80x86; unsigned multiplication of a byte (8 bits) from register or memory by the contents of the AL register with a word (16-bit) result in AX register, or unsigned multiplication of a word (16 bits) from register or memory by the contents of the AX register with a doubleword (32-bit) result in DX:AX register pair, or unsigned multiplication of a doubleword (32 bits) from register or memory by the contents of the EAX register with a quadword (64-bit) result in EDX:EAX register pair; uses an early out algorithm to speed up computations when possible; sets or clears flags
• IMUL Signed Integer Multiply; Intel 80x86; signed multiplication of a byte (8 bits), word (16 bits), or doubleword (32 bits) from register or memory by the contents of the EAX and EDX registers with result stored in the EAX and EDX registers, signed multiplication of a byte (8 bits), word (16 bits), or doubleword (32 bits) from register or memory by the contents of a register with truncated results (to size as operands) stored in the register, or signed multiplication of a byte (8 bits), word (16 bits), or doubleword (32 bits) from register or memory by the contents of an immediate value with truncated results (to size as operands) stored in any general register; uses an early out algorithm to speed up computations when possible; sets or clears flags
• MUL Multiply; MIX; multiply word or partial word field contents of memory to A-register (accumulator) with results stored in X-register and A-register pair, overflow toggle possibly set
• MR Multiply Register; IBM 360/370; RR format; signed multiply of the contents of an even numbered general purpose register (32 bits) by the contents of the immediately following odd numbered general purpose register (32 bits) with a 64-bit product in the register pair; register to register only; does not affect condition code
• M Multiply; IBM 360/370; RX format; signed multiply of the contents of a memory location (32 bits) by the contents of an odd numbered general purpose register (32 bits) with a 64-bit product in the register pair; main storage to register only; does not affect condition code
• MH Multiply Half-word; IBM 360/370; RX format; signed multiply of the contents of a memory location (16 bits) by the contents of a general purpose register (32 bits) with a 32-bit product (the high 8 bits of the true 48-bit product are discarded) in the register; main storage to register only; does not affect condition code
• EMUL Extended Multiply; DEC VAX; extended precision multiplication on operands in registers or memory, the first (longword) operand (multiplicand) is multiplied by the second (longword) operand (multiplier) giving a (doubleword) intermediary result which is stored in the fourth (doubleword) operand (product); clears or sets flags
• DIVS.W Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in memory or a register by a word (16 bits) in a data register with a result of the quotient (16 bits) in the lower word and the remainder (16 bits) in the upper word of the data register; clears or sets flags
• DIVS.L <ea>,Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in memory or a register by a longword (32 bits) in a data register with a result of a longword (32 bit) quotient in the data register and the remainder being discarded; clears or sets flags
• DIVS.L <ea>,Dr:Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a quadword (64 bits) in any two data registers by a longword (32 bits) in a data register with a result of the quotient (32 bits) in the second data register and the remainder (32 bits) in the third data register; clears or sets flags
• DIVSL.L <ea>,Dr:Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in a data register by a longword (32 bits) in a second data register with a result of the quotient (32 bits) in the first data register and the remainder (32 bits) in the second data register; clears or sets flags
• DIVU.W Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in memory or a register by a word (16 bits) in a data register with a result of the quotient (16 bits) in the lower word and the remainder (16 bits) in the upper word of the data register; clears or sets flags
• DIVU.L <ea>,Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in memory or a register by a longword (32 bits) in a data register with a result of a longword (32 bit) quotient in the data register and the remainder being discarded; clears or sets flags
• DIVU.L <ea>,Dr:Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a quadword (64 bits) in any two data registers by a longword (32 bits) in a data register with a result of the quotient (32 bits) in the second data register and the remainder (32 bits) in the third data register; clears or sets flags
• DIVUL.L <ea>,Dr:Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in a data register by a longword (32 bits) in a second data register with a result of the quotient (32 bits) in the first data register and the remainder (32 bits) in the second data register; clears or sets flags
• DR Divide Register; IBM 360/370; RR format; signed divide of the contents of a general purpose register pair (64 bits) by the contents of a general purpose register (32 bits) with a 32-bit quotient in the odd numbered register and a 32-bit remainder in the even numbered register of the register pair; register to register only; does not affect condition code
• D Divide; IBM 360/370; RX format; signed divide of the contents of a general purpose register pair (64 bits) by the contents of a memory location (32 bits) with a 32-bit quotient in the odd numbered register and a 32-bit remainder in the even numbered register of the register pair; main storage to register only; does not affect condition code
• DIV Divide; DEC VAX; arithmetic division of scalar quantities (8, 16, or 32 bit integer) in general purpose registers or memory, available in two operand (first operand [divisor] divided from second operand [dividend] with result [quotient] replacing second operand) and three operand (first operand [divisor] divided from second operand [dividend] with result placed in third operand [quotient]) (DIVB2 divide byte 2 operand, DIVB3 divide byte 3 operand, DIVW2 divide word 2 operand, DIVW3 divide word 3 operand, DIVL2 divide long 2 operand, DIVL3 divide long 3 operand); clears or sets flags
• EDIV Extended Divide; DEC VAX; extended precision multiplication on operands in registers or memory, the second (longword) operand (dividend) is divided from the first (longword) operand (divisor) giving the third (longword) operand (quotient) and the the fourth (longword) operand (remainder); clears or sets flags
• DIV Unsigned Divide; Intel 80x86; unsigned division of the accumulator by a byte (8 bits), word (16 bits), or doubleword (32 bits) divisor of half the size of the dividend in the accumulator, with the results stored in the accumulator (byte divisor: dividend is in the AX register, quotient in the AL register, and remainder in the AH register; word divisor: dividend is in the DX:AX register pair, quotient in the AX register, and remainder in the DX register; doubleword divisor: dividend is in the EDX:AEX register pair, quotient in the EAX register, and remainder in the EDX register); non-integral quotients are truncated to integers toward 0; sets or clears flags
• IDIV Signed Integer Division; Intel 80x86; Intel 80x86; signed division of the accumulator by a byte (8 bits), word (16 bits), or doubleword (32 bits) divisor of half the size of the dividend in the accumulator, with the results stored in the accumulator (byte divisor: dividend is in the AX register, quotient in the AL register, and remainder in the AH register; word divisor: dividend is in the DX:AX register pair, quotient in the AX register, and remainder in the DX register; doubleword divisor: dividend is in the EDX:AEX register pair, quotient in the EAX register, and remainder in the EDX register); non-integral quotients are truncated to integers toward 0; sets or clears flags
• DIV Divide; MIX; divide word or partial word field contents of memory from A-register (accumulator) and X-register (extension) pair with quotient stored in A-register and remainder stored in X-register, overflow toggle possibly set
• CMP Compare; DEC VAX; arithmetic comparison between two scalar quantities (8, 16, or 32 bit integer or 32 or 64 bit floating point) in general purpose registers or memory (CMPB Byte, CMPW Word, CMPL Longword); clears or sets flags
• TST Test; DEC VAX; arithmetic comparison of a scalar quantities (8, 16, or 32 bit integer or 32 or 64 bit floating point) in general purpose registers or memory (TSTB Byte, TSTW Word, TSTL Longword) to zero; equivalent to CMPs src, #0, but shorter and executes faster; clears or sets flags
• CMP Compare; Motorola 680x0, Motorola 68300; compares a register or contents of a memory location (8, 16, or 32 bits) to contents of a data register (data register minus effective address contents); clears or sets flags
• CMP Compare Two Operands; Intel 80x86; compares a register or contents of a memory location (8, 16, or 32 bits) to contents of a register or memory location (subtract of second operand from first operand with no storage of results, but setting or clearing of flags); clears or sets flags
• CMPA Compare A-register; MIX; compare word or partial word field contents of memory with same word or partial field of A-register (accumulator), set comparison indicator
• CMPX Compare X-register; MIX; compare word or partial word field contents of memory with same word or partial field of X-register (extension), set comparison indicator
• CMPi Compare I-register; MIX; compare word or partial word field contents of memory with same word or partial field of designated index register, set comparison indicator
• CMPA Compare Address; Motorola 680x0, Motorola 68300; compares a register or contents of a memory location (16 or 32 bits) to contents of an address register (adress register minus effective address contents); clears or sets flags
• CMPI Compare Immediate; Motorola 680x0, Motorola 68300; compares immediate data (8, 16, or 32 bits) to contents of a register or memory (effective address contents minus immediate data); clears or sets flags
• CMPM Compare Memory; Motorola 680x0, Motorola 68300; compares the contents of two memory locations (8, 16, or 32 bits) with a post increment of both address pointer registers (second location minus first location); clears of sets flags
• CMP2 Compare Register Against Bounds; Motorola 680x0, Motorola 68300; compares the contents of register (8, 16, or 32 bits) to a bounds pair (lower bound followed by upper bound), if both bounds are equal then this operation tests for a specific value; sets or clears flags
• CLR Clear; Motorola 680x0, Motorola 68300; clears a register or contents of a memory location (.B 8, .W 16, or .L 32 bits) to zero; clears flags for memory and data registers, does not modify flags for address register
• CLR Clear; DEC VAX; clears a scalar quantity in register or memory to zero (CLRB 8 bits, CLRW 16 bits, CLRL 32 bits, CLRQ 64 bits, CLRO 128 bits, CLRF 32 bit float, or CLRD 64 bit float), an integer CLR will clear the same size floating point quantity because VAX floating point zero is represented as all zero bits; quadword and D float clears of registers are consecutive register pairs, octaword clears to registers are four consecutive registers; equivalent to MOVx #0, dst, but shorter and executes faster; sets or clears flags
• STZ Store Zero; MIX; move word or partial word field of data, store zero into designated word or field of word of memory
• EXT Sign Extend; Motorola 680x0, Motorola 68300; sign extends a byte (8 bits) in a data register to a word (16 bits) or sign extends a word (16 bits) in a data register to a longword (32 bits); sets or clears flags
• EXTB Sign Extend Byte; Motorola 680x0, Motorola 68300; sign extends a byte (8 bits) in a data register to a longword (32 bits); sets or clears flags
• NEG Two’s Complement Negation; Intel 80x86; subtracts the contents of a register or memory (8, 16, or 32 bits) from zero and store the results in the original register or memory location (arithmetic negation or arithmetic inverse); sets or clears flags
• NEG Negate; Motorola 680x0, Motorola 68300; subtracts the contents of a register or memory (8, 16, or 32 bits) from zero and store the results in the original register or memory location (arithmetic negation or arithmetic inverse); sets or clears flags
• NEGX Negate with Extend; Motorola 680x0, Motorola 68300; subtracts the contents of a register or memory location (8, 16, or 32 bits) and the extend bit from zero and stores the results in the original register or memory location (multi-precision negation); sets or clears flags

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# free music player coding example

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