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division

summary

    This subchapter looks at division.

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stub section

    This subchapter is a stub section. It will be filled in with instructional material later. For now it serves the purpose of a place holder for the order of instruction.

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division

    This subchapter looks at division.

number systems

    Here is a little bit of college level work on division.

    A system of numbers os considered to be closed under an operation if it reproduces itself.

    S is a set of numbers. S is closed under division if for any two numbers a and b in the set S, the quotient a / b (provided b ≠ 0) is also a number in the set S. A set that is closed under division and does not include zero (0) is called a multiplicative group.

    The set of all positive real numbers is closed under division.

    The set consisting of only the single number zero (0) is closed under division, even though division by zero is excluded (because it still fits the definition). Because of this special exception, the term multiplicative group specifically excludes zero.

    A theorem regarding any set of numbers S, consisting of more than just the single number zero (0), that is closed under division, must have the following three properties:

    (a) S contains the number one (1)

    (b) When a ≠ 0 is a number in S the a^-1 is also in S.

    (c) S is always closed with respect to multiplication.

    The set of all positive and negative powers {1, a, a², …, a^-1, a^-2, …} for any number a ≠ 0 is a multiplicative group.

    A system of numbers that is closed under addition, subtraction, multiplication, and division is called a field. Because all systems closed under subtraction are also closed under addition and all systems closed under division are closed under multiplciation, a field can be defined as a modul in which all elements after the exclusion of 0 form a multiplicative group..

    Examples of fields are the set of only zero (a special case), the set of all rational numbers, the set of all real numbers, the set of all complex numbers, the set of all numbers of the form a + b√2 where a and b are integers, and the set of all numbers of the form a + b√D where D, a, and b are integers

assembly language instructions

    For most processors, integer arithmetic is faster than floating point arithmetic. This can be reversed in special cases such digital signal processors.

    On many processors, floating point arithmetic is in an optional unit or optional coprocessor rather than being included on the main processor. This allows the manufacturer to charge less for the business machines that don’t need floating point arithmetic.

    The basic four integer arithmetic operations are addition, subtraction, multiplication, and division. Arithmetic operations can be signed or unsigned (unsigned is useful for effective address computations). Some older processors don’t include hardware multiplication and division. Some processors don’t include actual multiplication or division hardware, instead looking up the answer in a massive table of results embedded in the processor.

• DIVS.W Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in memory or a register by a word (16 bits) in a data register with a result of the quotient (16 bits) in the lower word and the remainder (16 bits) in the upper word of the data register; clears or sets flags
• DIVS.L <ea>,Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in memory or a register by a longword (32 bits) in a data register with a result of a longword (32 bit) quotient in the data register and the remainder being discarded; clears or sets flags
• DIVS.L <ea>,Dr:Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a quadword (64 bits) in any two data registers by a longword (32 bits) in a data register with a result of the quotient (32 bits) in the second data register and the remainder (32 bits) in the third data register; clears or sets flags
• DIVSL.L <ea>,Dr:Dq Signed Divide; Motorola 680x0, Motorola 68300; signed division of a longword (32 bits) in a data register by a longword (32 bits) in a second data register with a result of the quotient (32 bits) in the first data register and the remainder (32 bits) in the second data register; clears or sets flags
• DIVU.W Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in memory or a register by a word (16 bits) in a data register with a result of the quotient (16 bits) in the lower word and the remainder (16 bits) in the upper word of the data register; clears or sets flags
• DIVU.L <ea>,Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in memory or a register by a longword (32 bits) in a data register with a result of a longword (32 bit) quotient in the data register and the remainder being discarded; clears or sets flags
• DIVU.L <ea>,Dr:Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a quadword (64 bits) in any two data registers by a longword (32 bits) in a data register with a result of the quotient (32 bits) in the second data register and the remainder (32 bits) in the third data register; clears or sets flags
• DIVUL.L <ea>,Dr:Dq Unsigned Divide; Motorola 680x0, Motorola 68300; unsigned division of a longword (32 bits) in a data register by a longword (32 bits) in a second data register with a result of the quotient (32 bits) in the first data register and the remainder (32 bits) in the second data register; clears or sets flags
• DR Divide Register; IBM 360/370; RR format; signed divide of the contents of a general purpose register pair (64 bits) by the contents of a general purpose register (32 bits) with a 32-bit quotient in the odd numbered register and a 32-bit remainder in the even numbered register of the register pair; register to register only; does not affect condition code
• D Divide; IBM 360/370; RX format; signed divide of the contents of a general purpose register pair (64 bits) by the contents of a memory location (32 bits) with a 32-bit quotient in the odd numbered register and a 32-bit remainder in the even numbered register of the register pair; main storage to register only; does not affect condition code
• DIV Divide; DEC VAX; arithmetic division of scalar quantities (8, 16, or 32 bit integer or 32, 64, or 128 bit floating point) in general purpose registers or memory, available in two operand (first operand [divisor] divided from second operand [dividend] with result [quotient] replacing second operand) and three operand (first operand [divisor] divided from second operand [dividend] with result placed in third operand [quotient]) (DIVB2 integer divide byte 2 operand, DIVB3 integer divide byte 3 operand, DIVW2 integer divide word 2 operand, DIVW3 integer divide word 3 operand, DIVL2 integer divide long 2 operand, DIVL3 integer divide long 3 operand) (DIVF2 divide float 2 operand, DIVF3 divide float 3 operand, DIVD2 divide double float 2 operand, DIVD3 divide double float 3 operand, DIVG2 divide G float 2 operand, DIVG3 divide G float 3 operand, DIVH2 divide H float 2 operand, DIVH3 divide H float 3 operand); clears or sets flags
• EDIV Extended Divide; DEC VAX; extended precision multiplication on operands in registers or memory, the second (longword) operand (dividend) is divided from the first (longword) operand (divisor) giving the third (longword) operand (quotient) and the the fourth (longword) operand (remainder); clears or sets flags
• DIV Unsigned Divide; Intel 80x86; unsigned division of the accumulator by a byte (8 bits), word (16 bits), or doubleword (32 bits) divisor of half the size of the dividend in the accumulator, with the results stored in the accumulator (byte divisor: dividend is in the AX register, quotient in the AL register, and remainder in the AH register; word divisor: dividend is in the DX:AX register pair, quotient in the AX register, and remainder in the DX register; doubleword divisor: dividend is in the EDX:AEX register pair, quotient in the EAX register, and remainder in the EDX register); non-integral quotients are truncated to integers toward 0; sets or clears flags
• IDIV Signed Integer Division; Intel 80x86; Intel 80x86; signed division of the accumulator by a byte (8 bits), word (16 bits), or doubleword (32 bits) divisor of half the size of the dividend in the accumulator, with the results stored in the accumulator (byte divisor: dividend is in the AX register, quotient in the AL register, and remainder in the AH register; word divisor: dividend is in the DX:AX register pair, quotient in the AX register, and remainder in the DX register; doubleword divisor: dividend is in the EDX:AEX register pair, quotient in the EAX register, and remainder in the EDX register); non-integral quotients are truncated to integers toward 0; sets or clears flags
• DIV Divide; MIX; divide word or partial word field contents of memory from A-register (accumulator) and X-register (extension) pair with quotient stored in A-register and remainder stored in X-register, overflow toggle possibly set

See also Integer Arithmetic Instructions in Assembly Language and Floating Point Arithmetic Instructions in Assembly Language

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