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synchronization

summary

    This subchapter looks at synchronization.

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stub section

    This subchapter is a stub section. It will be filled in with instructional material later. For now it serves the purpose of a place holder for the order of instruction.

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synchronization

    This subchapter looks at synchronization.

Ada

functions

PL/I    COMPLETION(event-name) — Pl/I built-in function that returns a '0'B if the event is incomplete and returns a '1'B if the event is complete. Event-name can be either an event element or an event array. In the case of an array argument the built-in function returns an array value.

assembly language instructions

    Multiprocessor instructions are used to coordinate activity between multiple processors.

    Some multiprocessor instructions are designed to allow the processors to communicate with each other. A test and set instruction is used to implement flags or semaphores between processors. A compare and swap instruction is used to implement more sophsticated communications between multiple processors (such as counters or queue pointers) or secure updates of shared system control data structures in a multi-processing environment. Interlocked instructions are used to update counters, flags, and semaphores while locking out any other processors or devices from changing or reading the memory location while it is being updated.

• TAS Test and Set an Operand; Motorola 680x0; tests the current value of the operand at the effective address in memory or a data register (obviously, data register operands aren’t multiprocessor, but the instruction still works) and sets or clears the N (negative) and Z (zero) condition codes accordingly, then sets the high order bit of the operand to one; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
• CAS Compare and Swap with Operand; Motorola 680x0; Compares the operand at an effective address in memory to a compare operand in a data register, if the operands are equal, the update operand is transferred from a data register to the original effective address, if the operands are unequal, the operand at the effective address is transferred to the data register that contained the compare operand; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
• CAS2 Dual Operand Compare and Swap; Motorola 680x0; Compares the operand at an effective address in memory to a compare operand in a data register, if the operands are equal, compares the operand at a second effective address in memory to a second compare operand in a data register, if the second operand is also equal, the update operands are transferred from a data register to the pair of original effective addresses, if either pair of operands are unequal, the operands at the pair of effective addresses are transferred to the data registers that contained the compare operands; this operation uses a read-modify-write memory cycle that completes the operation without interruption; sets or clears flags
• ADAWI Add Aligned Word Interlocked; DEC VAX; adds (16 bit integer) a source operand from a register or memory to a memory location that is word aligned while interlocking the memory location so that no other processor or device can read or write to the interlocked memory location, used to maintain operating system resource usage counts; and sets or clears flags

See also Multiprocessor and Coprocessor Instructions in Assembly Language

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